The present invention relates generally to electronic design automation (EDA) tools, and, more particularly, to an EDA tool for increasing fault coverage of an integrated circuit.
Integrated circuits (ICs) often include various analog and digital components. Such ICs may have manufacturing defects that are caused by dust particle contamination during fabrication, which can cause the ICs to malfunction. Thus, testing the ICs to detect such manufacturing defects is very important. Design-for-test (DFT) techniques add testability features to the ICs to check for and identify manufacturing defects. DFT enables automatic-test-equipment (ATE) to execute various fault tests on the IC. The ATEs use test patterns generated by test pattern generators such as, automatic test pattern generators (ATPG), pseudo-random pattern generators (PRPG), and so on, to detect faults in the ICs. The ICs that undergo such fault tests are referred to as circuits under test (CUT).
DFT enables detection of design faults of a CUT using automation, and hence reduces the time and cost required for development and execution of the fault tests. DFT techniques should provide coverage over all the design faults of the CUT. DFT techniques include various fault models such as transition, path delay, and stuck-at fault models. A transition fault model is used to detect a failure of a state transition at a particular element of the CUT that propagates through the CUT within a specific time period. A path delay fault model calculates a sum of delays at each element in a path within the CUT and detects faults by comparing the sum of delays of the path with a delay of a critical path. The stuck-at fault models such as, stuck-at ‘0’ and stuck-at ‘1’ fault models, are used to detect faulty connections between various elements of the CUT that cause a logic of the CUT to be stuck-at a particular logic state i.e., logic zero or logic one. Based on the source of the test patterns, DFT techniques are classified as either scan testing or built-in-self-testing (BIST).
Generally, scan testing is used for detecting design faults. The CUT, when subjected to scan testing, operates in two modes—a test mode (also referred to as shift operation) and a functional mode (also referred to as capture operation). At the beginning of the scan testing, the CUT is set in the test mode. In the test mode, the CUT is divided into multiple on-chip logic modules. Each on-chip logic module is further segmented into scan chains or paths. Digital logic elements (e.g., flip-flops, latches, and data registers) of an logic module are connected together to form scan chains or paths. The ATE serially scans a first test pattern generated by an ATPG into the digital logic elements of the scan paths. The CUT is then switched to the functional mode where the primary outputs of the CUT are observed and primary inputs of the CUT are set according to the functional requirement of the design of the CUT for one clock cycle of a clock signal of the CUT. The CUT is then switched back to the test mode and outputs of the scan paths are observed in each clock cycle. The ATE then loads a second test pattern into the scan paths when the previous test pattern is shifted out to a multiple input signature reader (MISR) for analysis. The process is repeated until required fault coverage of the CUT is met. The ATPG uses a gate-level representation of a netlist of the CUT to generate the test patterns and hence, the test patterns are deterministic. However, the ATPG does not have enough memory capacity to store an entire test set that covers all of the transition, path-delay, and stuck-at fault models.
BIST is a self-test mechanism provided to enable self-checking of logic within the CUT. For example, BIST procedures are often integrated in ISO 26262 standard compliant automotive electronic devices where testing of safety features is crucial. BIST is similar to scan testing, but uses a PRPG, such as a linear feedback shift register (LFSR), instead of the ATPG, for generating pseudo random test patterns. Since BIST does not require any additional equipment such as ATPGs for fault testing, BIST can be performed in the field (i.e., outside of the IC assembly house). BIST requires less time than scan testing to perform fault test methods, and hence, reduces manufacturing costs. However, the pseudo random test patterns that are applied to the CUT during BIST do not provide sufficient fault coverage and often miss hard to detect faults. To overcome the aforementioned disadvantages, ICs include observation and control test points. Observation test points are outputs of the logic elements that are used to detect faults and control test points are the inputs to the logic elements that are used to control the inputs.
EDA tools are used during the design stage of an IC, for example, for layout/floor planning of the various circuit components of the IC and the fault coverage requirements. FIG. 1A shows a schematic block diagram of a conventional IC 100 that is being structurally tested using observation and control test points. The IC 100 includes a first set of observation test points (A, B, C, D, E, F, G, and H) corresponding to outputs of a first set of logic elements (not shown) of the IC 100, first, second, and third XOR gates 102, 104, and 106, and a first scan flip-flop 108. First, second, third and fourth input terminals of the first XOR gate 102 are connected to the observation test points A, B, C, and D, respectively. An output terminal of the first XOR gate 102 outputs a first test signal. First, second, third and fourth input terminals of the second XOR gate 104 are connected to the observation test points E, F, G, and H, respectively. An output terminal of the second XOR gate 104 outputs a second test signal. The third XOR gate 106 has a first input terminal connected to the output terminal of the first XOR gate 102 for receiving the first test signal, a second input terminal connected to the output terminal of the second XOR gate 104 for receiving the second test signal, and an output terminal for outputting an observation test signal. The first scan flip-flop 108 is connected between the third XOR gate 106 and a second scan flip-flop (not shown) of a scan chain of the IC 100. The first scan flip-flop 108 has a data input terminal connected to the output terminal of the third XOR gate 106 for receiving the observation test signal, a scan input terminal for receiving a set of test patterns, a scan enable input terminal for receiving a scan enable signal, and a clock input terminal for receiving a clock signal. In an example, the set of test patterns can be generated by an ATPG (not shown) or a PRPG (not shown) when the IC 100 is undergoing testing using an ATE. In another example, the set of test patterns are generated internally by the IC 100 when BIST is invoked. An output terminal of the first scan flip-flop 108 is connected to the second scan flip-flop for outputting at least one of the observation test signal and the set of test patterns based on a logic state of the scan enable signal.
In operation, when the scan enable signal is high, i.e., during the shift operation of the IC 100, the set of test patterns are output at the output terminal of the first scan flip-flop 108. When the scan enable signal is low, i.e., during the capture operation of the IC 100, the observation test signal is output at the output terminal of the first scan flip-flop 108. Hence, required fault coverage of the IC 100 is met. However, the IC 100 includes multiple sets of observation test points and for each set of observation test points, an additional scan flip-flop is inserted in the scan paths. Therefore, the length of the scan paths increase, which increases the area overhead and the time required for testing the IC 100.
FIG. 1B shows another conventional IC 110 that is that can be tested using the observation and control test points. The first scan flip-flop 108 of FIG. 1A is replaced with a fourth XOR gate 112 and an AND gate 112. The IC 110 also includes a third scan flip-flop 116, which is a pre-existing scan flip-flop of the scan path. The AND gate 114 has a first input terminal connected to the output terminal of the third XOR gate 106 for receiving the observation test signal, a second input terminal for receiving an observation test point enable signal, and an output terminal for outputting the observation test signal. The fourth XOR gate 112 has a first input terminal connected to the output terminal of the AND gate 114 for receiving the observation test signal and a second input terminal for receiving a data input signal from a functional path of the IC 110. A data input terminal of the third scan flip-flop 116 is connected to an output terminal of the fourth XOR gate 112 for receiving one of the observation test signal and the data input signal based on logic states of the observation test point enable and observation test signals. A scan input terminal of the third scan flip-flop 116 receives the set of test patterns. A scan enable input terminal of the third scan flip-flop 116 receives the scan enable signal and the clock input terminal thereof receives the clock signal.
In operation, the observation test point enable signal is high during testing. When the scan enable signal is high, i.e., during the shift operation, the set of test patterns are output at the output terminal of the third scan flip-flop 116. When the scan enable signal is low during the capture operation, one of the observation test signal and the data input signal are output at the output terminal of the third scan flip-flop 116. The logic state of the observation test signal indicates whether the IC 110 is faulty or non-faulty. Thus, the output of the third scan flip-flop 116 indicates whether the IC 110 is faulty, and hence enables fault detection. Since the entire set of observation test points are covered by the test technique, the required fault coverage for the IC 100 is met. Since the third scan flip-flop 116 is an existing scan flip-flop of the scan path, no additional scan flip-flop corresponding to the first set of observation test points is required. However, the fourth XOR gate 112 adds a delay to the functional timing of the IC 100 during functional mode of operation.
Therefore, it would be advantageous to have an IC design with increased fault coverage and an EDA tool that can modify an IC design to generate an IC design having improved fault coverage but not increased area or functional timing.